1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a semiconductor integrated circuit which is suitable for improving a withstand surge voltage of an output circuit formed by high breakdown voltage field effect transistors.
2. Description of the Background Art
In recent years, a vacuum fluorescent display (VFD) or the like has been increasingly driven directly by the output from a micro controller unit (MCU) or a controller, and a semiconductor integrated circuit which contains a high voltage MOS transistor has been utilized as an output circuit for driving the same.
FIG. 6 shows a conventional output circuit for driving a VFD. As shown in FIG. 6, this output circuit comprises a high breakdown voltage p-channel MOS transistor 1 and a pulldown resistor 2 serving as a load. The p-channel MOS transistor 1 has a source and a bulk which are connected to a first power terminal 3, a gate which is connected to an input terminal IN and a drain which is connected to an output terminal OUT. The pulldown resistor 2 is connected between the drain of the p-channel MOS transistor 1 and a second power terminal 4. In general, a positive potential V.sub.CC of 5 V, for example, is applied to the first power terminal 3 from a high-potential power source, while a negative potential V.sub.P of -35 V, for example, is applied to the second power terminal 4 from a low-potential power source. A voltage of 0 to 5 V is applied to the input terminal IN as a control signal. A digit or segment of the VFD is connected to the output terminal OUT.
When the input terminal IN receives a high-level control signal of 5 V in this output circuit, the p-channel MOS transistor 1 is turned off so that the output terminal OUT receives the negative potential V.sub.P (-35 V) from the power terminal 4 and goes low. Thus, the VFD is not lit. When the input terminal IN receives a low-level control signal of 0 V, on the other hand, the p-channel MOS transistor 1 is turned on so that the output terminal OUT receives the positive potential V.sub.CC (5 V) from the power terminal 3 and goes high. Thus, the VFD is lit.
FIG. 7 is a sectional view schematically showing a semiconductor device implementing the output circuit shown in FIG. 6. As shown in FIG. 7, an n.sup.- -type well 6 for serving as the bulk of the p-channel MOS transistor 1 is formed on a first major surface side of a p.sup.- -type substrate 5. A p.sup.+ -type diffusion region 7 for serving as the source of the p-channel MOS transistor 1 and another p.sup.+ -type diffusion region 8 for serving as the drain thereof are provided on a surface side of the n.sup.- -type well 6 to be spaced apart from each other. An n.sup.+ -type diffusion region 9 is provided adjacently to the p.sup.+ -type diffusion region 7, while a p.sup.+ -type diffusion region 11 is formed adjacently to the other p.sup.+ -type diffusion region 8 through a field oxide film 10 to serve as the pulldown resistor 2. Further, a gate electrode 13 is formed on a region of the n.sup.- -type well 6 held between the two p.sup.+ -type diffusion regions 7 and 8 through an insulating layer 12. Thus, the p-channel MOS transistor 1 is defined by the n.sup.- -type well 6, the p.sup.+ -type diffusion regions 7 and 8, the insulating layer 12 and the gate electrode 13. The n.sup.+ -type diffusion region 9 and the p.sup.+ -type diffusion region 7 are connected to the first power terminal 3 to which the positive potential V.sub.CC is applied, while the gate electrode 13 is connected to the input terminal IN. Further, the p.sup.+ -type diffusion region 8 and an end of the p.sup.+ -type diffusion region 11 are connected to the output terminal OUT, while the other end of the p.sup.+ -type diffusion region 11 is connected to the second power terminal 4, to which the negative potential V.sub.P is applied. This semiconductor device operates in the manner described above with reference to FIG. 6, and hence redundant descrition is omitted.
While FIG. 7 shows the high breakdown voltage p-channel MOS transistor 1 in the structure of an ordinary transistor for convenience of illustration, a high breakdown voltage structure which is implemented by a well-known technique such as double diffusion is appropriately selected and employed for an actual device. However, the p-channel MOS transistor 1 of the ordinary structure is not substantially different in operation from that of high breakdown voltage structure except for the point of breakdown voltage characteristics, and hence the description will be made below with reference to the device of the ordinary structure shown in FIG. 7.
In the conventional semiconductor integrated circuit having the aforementioned structure, a parasitic diode 14 (see FIG. 6) is defined between the output terminal OUT and the power terminal 3 by p-n junction of the p.sup.+ -type diffusion region 8 and the n.sup.- -type well 6, as understood from FIG. 7. Therefore, it is necessary to consider the following surge countermeasure:
Consider that the output terminal OUT receives a plus (+) surge. In this case, a surge current is passed through a path along the output terminal OUT.fwdarw.the parasitic diode 14 (p.sup.+ -type diffusion region 8.fwdarw.the n.sup.- -type well 6.fwdarw.the n.sup.+ -type diffusion region 9).fwdarw.the power terminal 3, and hence a high withstand surge voltage is ensured.
Then, consider that the output terminal OUT receives a minus (-) surge. If the p-channel MOS transistor 1 is in an on state at this time, the surge current is passed through a path along the power terminal 3.fwdarw.the MOS transistor 1.fwdarw.the output terminal OUT, to cause no problem. However, if the p-channel MOS transistor 1 is in an off state, no electrical path for the surge current is defined since the impendance of the pulldown resistor 2 is generally set at a high level of several tens of K.OMEGA. in order to reduce power consumption. Consequently, the p-channel MOS transistor 1 is broken down and the surge current is passed through a path along the power terminal 3.fwdarw.the MOS transistor 1.fwdarw.the output terminal OUT. Thus, this semiconductor device has on extremely low breakdown voltage against the minus surge.
It may be considered to newly form a p-n diode in the n.sup.- -type well 6 to draw out the aforementioned surge current from the output terminal OUT to the power terminal 4 through the p-n diode. However, it is impossible to form such a p-n diode since the p.sup.- -type substrate 5 is connected to a GND potential in order to stabilize the operation of the transistor and the n.sup.- -type well 6 cannot be set at a potential lower than the GND level.
In general, therefore, the gate width of the p-channel MOS transistor 1 is widened to disperse heat generated by the transistor operation, to thereby increase the withstand surge voltage.
FIG. 8 shows a general withstand surge voltage measuring circuit using a capacitor charging method. In this measuring circuit, a switch 15 is switched toward a first transfer contact 15a to apply a voltage to a capacitor 17 from a power source 16, to thereby charge the capacitor 17, as shown in FIG. 8. Thereafter the switch 15 is switched toward a second transfer contact 15b to discharge charges from the capacitor 17 to a device 19 through a resistor 18, to examine a breakdown state of the device 19. The voltage applied to the capacitor 17 is sequentially changed to examine the breakdown state of the device 19, to thereby detect breakdown voltage of the device 19.
FIG. 9 shows a result obtained by setting the capacity of the capacitor 17 at C=200 pF and the resistance of the resistor 18 at R=0 in the measuring circuit shown in FIG. 8 and measuring breakdown voltage of the output circuit shown in FIG. 6 in practice. Referring to FIG. 9, the longitudinal axis represents the breakdown voltage and the horizontal axis represents the gate width of the p-channel MOS transistor 1. As understood from FIG. 9, the withstand surge voltage is increased with on increase in gate width a. Since the transistor size is increased in proportion to the gate width, large transistor size is required in order to attain a high withstand surge voltage. For example, an extremely large transistor size is required with a gate width of 2000 .mu.m, in order to ensure a withstand surge voltage of -300 V. When the gate width is thus widened, the current flowing in the transistor is increased. However, a segment drive for a VFD etc. generally requires a current of only several milliamperes, and hence such an increase of the current is wasted.